Dear All,

I want to write a verilog-A code which provides an arbitrary phase shift (which can be controlled as a parameter) of the actual o/p signal.

Is there any in-built function already available to do so? If not, how can I achieve this?

Regards
Sam.

You could use the absdelay() function. Unfortunately, Cadence's implementation does not work in the small-signal analyses. It has been that way for 14 years, so I guess they are not going to fix it.

It might help if you explained what you are trying to do. Verilog-A is a hardware description language, so it might help you to think about how you would implement this in hardware.

-Ken