The code was copied from designers-guide.org. So it should be correct.
I got several errors about the code and i do not know how to solve it.
I am using IC5141, mmsim61.
The errors i got:
Line 36
"for(i = bits-1; i >= 0; i = i-1 )<<--? begin"
Line 36
Error: In for-loop control, genvar expression can only consists of
integer constant or other unrolled genvar variables expression.
Line38
"result[i]<<--? = vdd;"
Error: Genvar variable `i' is referenced within incorrect for-loop.
Line41
"result[i]<<--? = 0.0;"
....
many more
Sound like those errors occurs whenever i use [i] or i
Is it my verilogA compiler too old? I am not sure how to check the version.
Code:`include "constants.vams"
`include "disciplines.vams"
module adc (out, in, clk);
parameter integer bits = 8 from [1:24];
parameter real fullscale = 1.0;
parameter real td = 0;
parameter real tt = 0;
parameter real vdd = 5.0;
parameter real thresh = vdd/2;
// resolution (bits)
// input range is from 0 to fullscale (V)
// delay from clock edge to output (s)
// transition time of output (s)
// voltage level of logic 1 (V)
// logic threshold level (V)
parameter integer dir = 1 from [-1:1] exclude 0;
// 1 for rising edges, 1 for falling
input in, clk;
output [0:bits-1] out;
voltage in, clk;
voltage [0:bits-1] out;
real sample, midpoint;
integer result[0:bits-1];
genvar i;
analog begin
@(cross(V(clk)-thresh, +1) or initial_step) begin
sample = V(in);
midpoint = fullscale/2.0;
for(i = bits-1; i >= 0; i = i-1 ) begin
if(sample > midpoint) begin
result[i] = vdd;
sample = sample - midpoint;
end else begin
result[i] = 0.0;
end
sample = 2.0*sample;
end
end
for (i = 0; i < bits; i = i + 1) begin
V(out[i]) <+ transition(result[i], td, tt);
end
end
endmodule