I'm running a transient simulation, using spectre MMSIM72, on a circuit with several CMOS inverters in a chained configuration.  Input is isolated from output.

The compact model for the FETs is the VerilogA PSP 102.3 model which I have modified to significantly reduce the capacitance contributions.  There's no other components in the circuit.

As the length of the inverter chain increases, the total current consumption as well as the output voltage waveform become increasingly unstable.

For example, when completely removing all capacitance so that I have a purely resistive circuit, the transient simulation will produce anticipated results for 2 inverters. At 3 inverters logic levels start to become unrealistic. At 10 inverters, the simulation fails due to convergence problem.

Generally speaking, the trend is that the smaller the capacitance is, the smaller a circuit the simulator can handle before failing due to convergence problem.

I see the same trend in Hspice. I also observe this with other compact FET models.

Is this is a simulator problem?

If so, would it make more sense to run SpectreAMS or Spectre APS on a purely, or very near, resistive type of circuit where I'm mainly interested in determining the logic states and current consumption in the various [stabilized] logic states?

I'm running on a Linux RedHat system.

---Michael Olsen

Thanks for the answer.

Fyi, the aim of my project is to accurately estimate DC currents of large complex circuits as fast as possible using various VerilogA FET models.

What you're saying about AMS simulators, I've heard from others as well.  AMS sim is fast but not accurate in terms of current prediction. But maybe I could use this to at least get the coarse logic levels and currents and which I subsequently might use as input to a DC analysis. Can this be done?

Wrt DC sweep, will this work with multiple sweep "stimuli" which would mimic the toggling of a circuit's logic states in the same fashion that a transient analysis would?  


---Michael