We need to design a comparator which has a switching voltage of 1mV. As of now, the offset required between the two inputs is 4mV. How should I go about reducing this to 1mv? Further, I have a doubt here.. won't the supply noise or process variation affect this offset voltage ?

Thanks,
Kanu

One more question.. I was just wondering will it be good idea to design opamp for this comparator instead of using a comparator circuit ? What I mean to ask is that since both comparator and opamp have input stage of differential amplifier... will I require to scale opamp too by 16X ?

I applied voltages of 0.604V and 0.6V to the two inputs of the differential amplifier of the comparator (though I guess.. this is not enough and I will need to run monte carlo simulation to say for sure). What actually I mean is that our project needs higher sensitivity for the comparator, ie, it should be able to detect the difference between the inputs which is as low as 1mV. Do correct me if you think that my methodology is incorrect.

For the comparator circuit, I actually used one of the comparator circuit given in Dr. Baker's book. I modified it to work for 1.2V supply and 90nm. Finally, the circuit consumes power of 320uW (which I may need to reduce further..probably by compromising on current and slew rate)

Further, as mentioned in above post I increased Ws by 4 times of input transistors. It did take switching voltage down to 2mV without considerable increase in power.

Now, as mentioned in the book I was trying to increase the transconductance of the input transistors to see the effect ( I am not sure how is it going to affect the power though).

I will appreciate if I can get any help.

So, does that mean even opamp isn't good enough ? Is this because of process variation and supply voltage noise ? or its only that 1mV offset is not possible along with low power ? Please suggest something. I think I am lost  :(

hi, what i mean is in analog compensation you have to put into loop and store some where in a cap and subtract in the next phase. Where as in digital calibration you will blindly pump some programmable current and make both legs of diff pair balanced with this you will get very nice control across Monte Carlo also. I have implemented this in one my work. if you want to see basic implementation refer the following pap (i have written this)

High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique

Thanks,
rajasekhar.

I see.. I get the problem. I did some reading on systematic and random offsets. I will try to reduce systematic offset.

Raja, I will appreciate if you can send me your paper. I tried to access through our online library but could not get it.

Thanks all for help.

May I ask why analog techniques are not good enough to get to 1mV offset?

It is true that you have to think of influence of charge injection/CLK feedthrough of the switches that are connected to a sampling capacitor. However, these are not random offsets any more, right?

IF chopping is used instead of CDS or AZ residual offsets as low as 20uv can be achieved. This is way smaller than 1mv.
Commercial autozero opamps (which are chopper stabilized and not autozero really) have actually those input referred offset.
So 1mv is can be way reduced with analog techniques like chopper stabilization.

Best
Tosei