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cannot filter out short pulses (Read 768 times)

Pavel

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Posts: 174
Lausanne/Switzerland

cannot filter out short pulses
Jul 27^th, 2010, 12:50am

Hello,

I want my latch to filter out short pulses (shorter than 0.15ns).
But in spite of standard it doesn't. Here is code:

Code:

`timescale 1 ns / 1 ps

module Latch(nD, nGate, Q);
 �input nD, nGate;
 �output reg Q;
 �
 �always @(nGate, nD)
 � � �if(nGate == 0) Q <= ~nD;
 � � �else Q <= Q;
 � � � �
 �specify
 � � �specparam tRise_nGate_Q = 0.15, tFall_nGate_Q = 0.2;
 � � �(negedge nGate *> (Q+:nD)) = (tRise_nGate_Q, tFall_nGate_Q);
 �endspecify

endmodule

Where is my mistake ?

Thanks,

Pavel.

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Marq Kole Senior Member Offline Hmmm. That's weird... Posts: 122 Eindhoven, The Netherlands	Re: cannot filter out short pulses Reply #1 - Aug 3^rd, 2010, 7:17am You might want to have a look at the PATHPULSE$ specparam (section 14.6.1 of the 1364-2005 IEEE Verilog LRM) which explains how to filter out short pulses with the specify block. Cheers, Marq
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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: cannot filter out short pulses Reply #2 - Aug 3^rd, 2010, 10:37am I tend to use the inertial delay of the continuous assignment statement to filter out short pulses. You might want to try that. -Ken
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