Hello,

Looking at the main risk in buck converter design, I found the ground noise as most risky.
Using Epi wafer, and assuming I place many Taps, I still can't see the risk if the rise time and fall time of LX (inductor node) are ~10nS.
Questions:
1) I know that during the dead zone there will be forward diode driving current to the bulk but what is the risk here?
2) Did some one failed 1.5Amp buck design in CMOS because of this substrate current or because of switching voltage noise?

Thanks,
Erez