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Link a netlist to a layout for LVS and simulation (Read 11211 times)
aaron_do
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Link a netlist to a layout for LVS and simulation
Aug 23rd, 2010, 8:42pm
 
Hi all,

this is related to my previous topic, but I want to ask this separately just to avoid any confusion. Basically I have created a SPICE netlist of a center-tapped inductor using ADS. The netlist is shown below (the file name is 3_PORT.cir)

I originally did the layout of the inductor in Virtuoso, and now I want to link this netlist to a symbol and the layout so that I can use this inductor as if it were an inductor from my PDK...i.e. it should be able to pass LVS, and be instantiated in a schematic for simulation in ADE. So how do I do this? The best I could find is the link below,

http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how...

but i'm not sure that its relevant. Anyway I couldn't get it to work. Can anyone please tell me how I can get this done? I don't believe it is that difficult...

Note that this netlist is quite simple. I'll generate a more accurate one if necessary later...

thanks,
Aaron


Quote:
SPICE 2G6 netlist generated from [S] parameters

.subckt 3_PORT 1 2 3
* L in nH, C in pF
R1  1  0  5755.04888704202  
C1  1  0  0.0216441537364164P
C2  1  2  0.254276980705922P
R2  2  0  5916.61612055921  
C3  2  0  0.0209698166681806P
R3  3  0  27976.2145075654  
C4  3  0  0.032643729681058P
R4  1  6  3.51165320272679  
L1  6  3  0.458570933771721N  
R5  2  8  3.56845501963307  
L2  8  3  0.462151170377161N  
.ENDS
* end of sub-circuit


btw here is the error I got when I tried to use the method in the link.

Quote:
sevNetlistAndRun('sevSession1)
Delete psf data in /usr2/tmp/PowerGain_diff/spectre/schematic/psf.
generate netlist...
Begin Incremental Netlisting Aug 24 11:41:37 2010
*Error* ilGetString: arg must be symbol or string - 1
<<< Stack Trace >>>
(... in nlPrintInstSignals ...)
(... in nlPrintInst ...)
(... in _nlPrintInstInContext ...)
(... in nlNetlistFileInstOutput ...)
apply('nlNetlistFileInstOutput _artAliasArg_)
(... in hnlProcInst ...)
hnlProcInst('(db:0xb77333a0 db:0xb4b75992 0 1 ("net077" "net076" "net075") ... ))
(... in hnlPrintDevices ...)
hnlPrintDevices()
(... in hnlPrintMacroCell ...)
hnlPrintMacroCell()
skillEvalString("hnlPrintMacroCell()" nil)
(... in hnlDoInstBased ...)
(... in hnlPrintNetlist ...)
(... in hnlRunForkedNetlister ...)
hnlRunForkedNetlister()
skillEvalString("hnlRunForkedNetlister" nil)
...
ERROR (ADE-6026): Unable to create the netlist due to failure of following operating system command(s)
      "sh: ./.control: Text file busy"
      Contact your system administrator for assistance.
     ...unsuccessful.
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Tawna Wilsey
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Re: Link a netlist to a layout for LVS and simulation
Reply #1 - Aug 24th, 2010, 11:30am
 
Hi Aaron,

This is a super quick reply, as I'm in the middle of a project...

This error you are seeing typically indicates that there is an issue with the CDF.
I am assuming that you are using IC6.1.4 (as opposed to 5.1.41).  

I created a netlist using your inductor snippet -- see below.  (I put it in a format so I could easily simulate in spectre):


-----------------------------

simulator lang=spectre
subckt three_port 1 2 3

simulator lang=spice

* L in nH, C in pF
R1  1  0  5755.04888704202
C1  1  0  0.0216441537364164P
C2  1  2  0.254276980705922P
R2  2  0  5916.61612055921
C3  2  0  0.0209698166681806P
R3  3  0  27976.2145075654
C4  3  0  0.032643729681058P
R4  1  6  3.51165320272679
L1  6  3  0.458570933771721N
R5  2  8  3.56845501963307
L2  8  3  0.462151170377161N
* end of sub-circuit

simulator lang=spectre
ends three_port

------------------------------
I edited the CDF as noted in the link


http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how....

(Note:  this was written for IC5.1.41 but the basic idea is the same)

Here is a snippet (not the complete) CDF for the inductor symbol:
/****************************************************/
LIBRARY = "testcase"
CELL    = "Aaron_inductor"
/****************************************************/

let( ( libId cellId cdfId )
   unless( cellId = ddGetObj( LIBRARY CELL )
       error( "Could not get cell %s." CELL )
   )
   when( cdfId = cdfGetBaseCellCDF( cellId )
       cdfDeleteCDF( cdfId )
   )
   cdfId  = cdfCreateBaseCellCDF( cellId )

   ;;; Parameters
   cdfCreateParam( cdfId
       ?name           "model"
       ?prompt         "model name"
       ?defValue       ""
       ?type           "string"
       ?parseAsCEL     "yes"
   )

   ;;; Simulator Information
cdfId->simInfo->spectre = '( nil
       modelParamExprList nil
       optParamExprList  nil
       opParamExprList   nil
       stringParameters  nil
       propMapping       nil
       termMapping       nil
       termOrder         ("1" "2" "3")
       componentName     nil
       instParameters    (myParameters)
       otherParameters   (model)
       netlistProcedure  nil
   )

   ;;; Properties
   cdfId->formInitProc            = ""
   cdfId->doneProc                = ""
   cdfId->buttonFieldWidth        = 340
   cdfId->fieldHeight             = 35
   cdfId->fieldWidth              = 350
   cdfId->promptWidth             = 175
   cdfId->instNameType            = "schematic"
   cdfId->instDisplayMode         = "instName"
   cdfId->netNameType             = "schematic"
   cdfId->termSimType             = "DC"
   cdfId->termDisplayMode         = "netName"
   cdfId->paramSimType            = "DC"
   cdfId->paramDisplayMode        = "parameter"
   cdfSaveCDF( cdfId )
)

I was able to instantiate the inductor subckt in the schematic and run an sp simulation.

If you continue to have issues with this, please contact Cadence Customer Support ( support.cadence.com ) so we can help you out.

best rgards,
Tawna Wilsey

Cadence Design Systems
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Tawna Wilsey
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Tawna Wilsey
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Re: Link a netlist to a layout for LVS and simulation
Reply #2 - Aug 24th, 2010, 11:38am
 
Hi Aaron,

One more thing...the error message  (Error ADE-6026) that you get is pretty cryptic and doesn't point the real issue.  It should point you to issues in the CDF rather than spit out:

ERROR (ADE-6026): Unable to create the netlist due to failure of following operating system command(s)
     "sh: ./.control: Text file busy"
     Contact your system administrator for assistance.
    ...unsuccessful.

Please contact Cadence Customer Support ( support.cadence.com ) so we can file a CCR on your behalf to have the error message improved.



best regards,
Tawna Wilsey
Cadence




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Tawna Wilsey
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aaron_do
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Re: Link a netlist to a layout for LVS and simulation
Reply #3 - Aug 24th, 2010, 5:32pm
 
Hi Tawna,


thanks for the reply. I'm not really sure exactly what I should do at this point, however. I suppose I can try and redo the CDF editing and see if I got any of the parameters wrong. But my main concern is really how can I link a schematic to a layout so that it passes LVS? If I simply create a schematic of the netlist, and then draw the inductor, it will fail LVS because the schematic looks nothing like the layout.

Any help is appreciated,

thanks,
Aaron
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Tawna Wilsey
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Re: Link a netlist to a layout for LVS and simulation
Reply #4 - Aug 24th, 2010, 5:35pm
 
Hi Aaron,

RE: what to do ....
I recommend contacting Cadence Customer Support ( support.cadence.com ) for your question.  I can help you with the front end (simulation/netlisting) questions.  I just don't have a lot of experience with the LVS part.

best regards,
Tawna Wilsey
Cadence
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Tawna Wilsey
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