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PLL settling time measurement (Read 6346 times)
rfmems
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PLL settling time measurement
Sep 15th, 2010, 12:53am
 
I used to measure PLL setting time with extrapolation, which is, measuring the time it needs to settle to 100KHz, then 10KHz, then calculate the time it needs to settle within 1KHz, 100Hz, with the assumption that the frequency error decays exponentially.

I am wondering, if it is really possibible to measure the setlling time accurately to the resolution of 1KHz or 100Hz, with a SSA for example?
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pancho_hideboo
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Re: PLL settling time measurement
Reply #1 - Sep 15th, 2010, 8:34am
 
rfmems wrote on Sep 15th, 2010, 12:53am:
I am wondering, if it is really possibible to measure the setlling time accurately to the resolution of 1KHz or 100Hz, with a SSA for example?
I can measure it with such resolution by using Tektronix RSA6100 Real Time Spectrum Analyzer.
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rfmems
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Re: PLL settling time measurement
Reply #2 - Sep 15th, 2010, 8:47am
 
Thanks pancho,  I think the instrument itself will introduce delay due to the high resolution, is that negligible in your case?
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pancho_hideboo
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Re: PLL settling time measurement
Reply #3 - Sep 15th, 2010, 8:59am
 
rfmems wrote on Sep 15th, 2010, 8:47am:
I think the instrument itself will introduce delay due to the high resolution, is that negligible in your case?
System delay is known.

Rather than it, most severe issues are a rise time of trigger signal and threshold setting of external trigger input of instruments.
These largely affect start time.
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« Last Edit: Sep 15th, 2010, 12:11pm by pancho_hideboo »  
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rfmems
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Re: PLL settling time measurement
Reply #4 - Sep 17th, 2010, 2:55am
 
Hi Pancho,

I am a little confused here.

I guess if a frequency resolution of 100Hz is desired, then won't it take at least tens of ms to achieve that? And won't it be too slow to measurement pll settling which is below 100us?

In my case, trigger seems to be a much less problem, but then it depends on how the chip is controlled and so on.
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pancho_hideboo
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Re: PLL settling time measurement
Reply #5 - Sep 17th, 2010, 8:15am
 
rfmems wrote on Sep 17th, 2010, 2:55am:
I guess if a frequency resolution of 100Hz is desired,
then won't it take at least tens of ms to achieve that?
And won't it be too slow to measurement pll settling which is below 100us?
No.
But response time of instruments will be very slow.
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love_analog
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Re: PLL settling time measurement
Reply #6 - Oct 11th, 2010, 6:44am
 
I am curious - how do you measure PLL settling time.
a) What instrument do you use
b) What stimulus do you give

I would think you apply a phase step and look at the phase settling of the output but I haven't seen any instrument do so.
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