Hi there,　i'm digital engineer.

Plz let me know about how 2 coding verilo-AMS.

Now i make test bench for checking inout I/O behavior.
For checking output behavior of I/O,
test bench which is connected to this I/O have to stop driving
like as tri state buffer of Logic  for checking I/O's output signal.

now my test bench was made by Verilog-D coding,
and DUT had 5V I/O (analog schematic design).

in this case, i should change digital 2 Analog converter
like here


module DAC_ams( Din , A5vout );

input  Din;
output A5vout;

electrical Din,A5vout;

real temp;

analog begin
@(cross(V(Din)-0.7,0));
  if(V(Din)>0.1) temp = 1;
  else temp=0;

V(A5vout) <+ 5*transition(temp,0,1n,1n);

end

endmodule


when Logic test bench drive Hiz, this module stop driving too.

plz let me know how 2 correct this module for this aim ?

sheldon wrote on Sep 27^th, 2010, 1:26am:


thx Sheldon,

i wana make correction only one point.

Din is Digital signal.
And we define L2E on other system 1.5v(D1),0v(D0) on tran 0ns.
thus, when Din goes to high, V(Din) reached 1.5v and
                Din goes to low, V(Din) reached 0v A.S.A.P.

this function model works fine now.


so how 2 add function Hiz-State by Analog solver(Verilog-AMS) ?

how about bellow way ?


I can make enable logic signal for driving or not. as ENABLE is set.

analog begin
@(cross(V(Din)-0.7,0));
  if((V(Din)>0.1) & ENABLE ) temp = 1;
  else if( ENABLE ) temp=0;

V(A5vout) <+ 5*transition(temp,0,1n,1n);

end





i know , i should try myself at first.
but i can't. cos i'm not so familiar w/t Analog tool Environment.

now , i'm making test bench on Analog tool Environment.


plz give me kindly help and advice.