HI RFICDUDE,
Agree with all your other points.
Quote:Vgs for the CG stage will increase due to the decreased width (increased current density since the current is set by the CS device), so the gate voltage should be higher to maintain the same Vds bias for the CS stage. The higher gate voltage may result in lower P-1dB gain compression point of the LNA.
Normally in many designs, the gate of the CG stage is connected to VDD and there is no special biasing scheme for this node. Now I would have thought that higher the gate voltage, it would result in more linearity. One line of thought (and something that could be faulty) is that lower the gate voltage, lower will be the permissible voltage swing at the drain of the CS stage and the incoming signal would start getting clipped/compressed sooner.
Taking this line of thought to its extreme, where the gate voltage on the CG stage is so low that the CS stage is essentially operating in the linear regime. Now in this case, linearity is pretty good but gain has come down substantially.
I think whether linearity is improved or worsens depends on a lot of factors,