Device Sizing in Cascode Stage:
The cascoded stage provides a reasonably low (about 3
dB) noise figure. One relationship reducing NF should be
mentioned. If the body effect is absent then the width of the
cascoding transistor M2, should be chosen three times less
(this ratio may slightly vary during simulations) than that of
the input transistor M1. It is contrary to the common practice
to use the devices of the same width and may be used when the
transistors are in separate wells.
          Can anyone explain why it is so?

Thank U
saam

Saam,

The main reason for the cascode is to increase output resistance, but to increase ouput resistance while decreasing output capacitance is a bonus not to be passed up. Im with raja use the smallest device you  can get away with.

http://rfcooltools.com

Hmm, I find these comments interesting because of the following reasons:

1. I was raised to believe that an important benefit of cascoding is extending the high frequency bandwidth by reducing the Miller Effect multiplication of Cgd referred to the input resulting from the inverted voltage gain between the drain and gate. For LNAs the improved high frequency gain certainly has some benefit for input referred noise and also some impact on the input impedance.

2. Decreasing the width of the common gate device raises the load impedance at the interface between the CS and CG stage, so the voltage swing is higher at this node (as mentioned in #1). I would think, but I don't know for sure, that this would have some impact on linearity.

3. Vgs for the CG stage will increase due to the decreased width (increased current density since the current is set by the CS device), so the gate voltage should be higher to maintain the same Vds bias for the CS stage. The higher gate voltage may result in lower P-1dB gain compression point of the LNA.

I apologize for not answering the original question regarding the 3:1 width ratio. I would have to do a little analysis to figure out what the benefit is.

Yes, higher CG gate voltage improves the linearity of the CS stage; although any headroom above what is needed for the gain to the CG-CS interface is pretty much wasted. Keep in mind the voltage gain to this interface should be small (proportional to gm_cs/gm_cg).

However, making the CG device narrower will increase its Vgs for the same current, so Vs has to decrease (since Vg=Vdd) which lowers Vds on the CS device.

Also, setting Vg=Vdd for the CG device means the peak output swing is limited to Vt (assuming an inductor load) since Vd can only drop below Vg by Vt before the CG device falls into triode. This can also have a limiting effect on the input referred linearity.

Hello
      Thank You for the valuable information provided..
      From the information as simply i understood that , cascode device is mainly used to avoid miller effect and to improve the gain...also in this if we choose proper cascode device sizing we can obtain the required bandwidth.
      Currently i am designing this resistive feedback LNA(the circuit which i have attached ) for 2-6GHz frequency range. But this circuit is from 2-11.2GHz wide band.
     So for my design i used series LC circuit parallel with active inductor...so i got gain only for 2-6GHz, but problem is that i am getting input matching only for 3-6GHz.
     I am not able to find which parameter i have to vary to move S11 upto 2GHz.(towards left)...with gain tradeoff.
     Can anyone help me....
Thank You
Saam

I am attaching the designed circuit and waveforms for S21 and S11..please find