Hi all,
Thanks for your attention.
I have a problem about spectre-verilog simulation in a hierarchical circuit. This hierarchy includes schematic (MOS,R,L,C), verilog-A RTL, and verilog RTL, which is shown in attached figure 1.
The top cell is created by hierarchy editor as a config view, and set up the mix-signal partition and interface correctly.
The problem is when I correctly set the input of Vin (pulse signal), Clock (pulse signal), and register input (logic high/low), the verilog RTL output is always zero. This is found that the verilog code were not operated correctly by input signal, and was debugged by following way, which is shown in figure 2.
We descend the top cell and disconnect the input signal to verilog, and create the same source inside the top cell for verilog. Then the verilog output is correct this time.
Does anyone know if there is any limitation in spectre-verilog simulation about hierarchy, please kindly advice me, thanks.
Daniel