Now , i'm using Cadence's  AMS Designer.

DUT was made by schema.
Modules of Test bench were made by Verilog-D or AMS.
TOP block of Test bench was made by schema.

So, i try to add System Verilog Assersion to Test Bench.

And so, i have one problem which are depending on
w/ or w/o bind function on System Verilog.

1) making System Verilog code w/o bind
No Error on compiling and runs well that assersion

like this

   property pr_001; @(posedge TESTBENCHTOP.I13.a)
       !TESTBENCHTOP.I13.b |=> TESTBENCHTOP.I11.D8out == 8'h00 ;
   endproperty


2) making Sytem Verilog code w/t bind
Error occured on compilation

like this bind function of System Verilog

bind TESTBENCHTOP sva_monitor sva_monitor(
   .CLK(I13.a),
   .RST_X(I13.b),
   .DOUT(I11.c)
   );



anybody, plz let me know how to the best way for..