I'm doing some research on current reference schemes.  I've seen the following two schemes:  Both utilize a BGR/VREF to generate a gate bias

1.  NMOS biased at ZTC (zero-tempco point), where mobility and vth variation cancel each other.  

2.  NMOS in series with opposite tempco resistor -- NMOS has positive tempco resistance balanced with negative tempco resistor.

What are the pros/cons of the two schemes?  Any pointers to references/papers appreciated.