Geoffrey_Coram wrote on Nov 4th, 2010, 5:54am:I don't know what "trans" means -- transparent? translated?
@Geoffrey_Coram
thx for your correction. that means "translated".
sheldon wrote on Nov 5th, 2010, 3:34am:Sand Dolphin,
Your post was not very clear but it seems that you may have
confused using schematics with using schematics of transistor level
designs. Certainly using transistor level schematics is not top down
design. However, using schematics can be the basis for top down
design.
@sheldon
thx for your good advice and letting me Candence's info...
and i know the better way to use verilog-AMS.
like as on page 4,5 of Cadence's pdf file which u linked.
So ,
I want to make Turn around Time
shorter
to make TOP design and Test bench too not only easy simulate system level behavior and quality.
So , basically i want to consider bellow situation
In case of team was configured from
-
many Analog engineers ( only know bottom up design flow )
they can't make behavior models of their designs.- some Digital engineer ( only know top level design flow )
- chip is not so big system, but routing signals of TOP are so many.
and, Analog engineers are so busy
to build transistor based design and lay out chip.
then, they have no time to make top design on early stage
and can't simulate as top level system.
Now
we try to make Digital engineers help to
build and lay out and simulate Top design which is made from
-some analog design macro's(are made by bottom up designer)
-and one Logic blocks(is made by top down desinger).
then, i make this thread to
easily making TOP design and test benches
and trying TOP lay out for Digital Engineers.
so i think,
this thread do not care for top level or not as for making chip.
cos analog macros are building by Analog engineers at starting stage...
and thye can't build Analog macros by top down ....So, in this case
Is there No advantage for using verilog-AMS for top design ???
plz feel free asking to me....
.