Hi all,

I have a sub-cell layout with separated bulk and GND routings. So the source and bulk for all NMOS is routed separated and both lines have different netnames. Now there is a p-well that is conneted to the GND line and Assura sees that as a soft connect between bulk and GND (which in fact it is) and this generates errors.
Is there a way to connect these two nets just for LVS checks and not in the layout?
Is there a function where I can connect the GND-net with the bulk-net? I know the "joinablenet" function but this only works for nets with the same name.

Thanks for your help!

Hi Bernd,
Sorry for the late reply. I wasn't aware of your response. (forgot to activate the notification  :-[ ).

Does this mean that the nets in the layout as well as in the schematic are renamed for the checks (but not in the actual schematic and/or layout)? Or does it only work for the layout side of the design?