Steve,

Most books and theses that cover Pipelined ADC design will help you here.  In particular, read the PhD theses of Abo and Chien, they are classics and go through the derivations of the different components.

To answer your question, you can write out the gain equation for a Pipeline stage and see that, given high op-amp open-loop gain, the caps need to match to at least 1/2 LSB at the accuracy of the resolution remaining after the first stage (this statement is valid in multibit or single-bit first stages).  So, if you have have a 12b ADC with a 1.5b first stage, the deltaC/C needs to be less than 1/2 times 11bit-accuracy, or 1 part in 4096.  (You also have to multiply this by one over the feedback factor, see the theses I mentioned for the explanation).

If caps of this accuracy slow down the stage or make it use too much power you can use a mulit-bit first stage or look into calibration.  The place to start for that subject is the paper by Karanicolas.

Carl