hi,
for DDR3 in 65nm  i am designing one ring oscillator based PLL i have chosen mennetis delay cell based ring oscillator but its giving 7g Kvco. I tried many ways to reduce this but i am not able to go significantly  below. So i just want to know for  1g to 1.8g range will this architecture gives lower Kvco? other can any one suggest some god architecture which gives less Kvco like 2 to 3G.

Thanks.