carlgrace wrote on Dec 7th, 2010, 4:27pm:RobG wrote on Dec 7th, 2010, 5:41am:Isabelle wrote on Dec 7th, 2010, 3:07am:Hello,
The simplest solution might be to connect the available bandgap voltage directly to a PMOS device with a really small W/L ratio to lower its gm. Since the AnalogDE's accuracy requirements are very loose, that may be good enough, even with PVT variations.....
Hi Isabelle,
Yes, that has been suggested by Carl and myself (but I suggested an NMOS). I'm curious how you or Carl would connect the PMOS. With an NMOS it is simple: Gate to Vref, and source to GND, and take the current from the drain. But how would you connect a PMOS?
rg
Rob,
It totally depends on the VDD range and whether AnalogDE needs to source or sink a current. For example, if the BG voltage is 1.1 V, for instance, it might be challenging to keep an NMOS under control with such a large VGS. If VDD where 1.8 V, for instance you could connect it like you suggested AnalogDE connect the NMOS: Vref to gate, source to VDD, drain to load. Either way works, depending on the situation.
AnalogDE said the plan was to go with the weak NMOS. I think it will work.
Oh, ok. I don't like doing stuff like that (even though it was strongly endorsed by a lady selling dogs
). The reason is that Vref is bypassed to ground so any AC power supply noise appears across the PMOS gate/source and gets put onto the current (I
ac=g
m*V
noise). Most applications can handle the variation with Vdd, but not the AC noise, especially when mismatches are considered.
The larger Vgs is actually an advantage since it lowers the g
m. It also steers the temp co towards PTAT, which is better for most circuits. There is also a point where the temp co is zero. This point has been around Vgs=1.2 V when I've played with it, although I'm sure it depends on the Vt of the device.
Adding resistive degeneration decreases the g
m even more.
That's my story, and I'm sticking to it :P .
Rob
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No I don't sell dogs.