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Integrating limits for jitter (Read 3785 times)
raja.cedt
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Integrating limits for jitter
Dec 07th, 2010, 5:34am
 
hi all,
while integrating closed loop phase noise to get RJ, integration limits depends on the application and i am designing PLL for serial IO application, based on people suggestion i used to integrate from 12k to 20Meg. but i want to know clearly on what basis we have to select these limits. can any body please help or Please direct me to a proper reference.

Thanks.
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Mayank
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Re: Integrating limits for jitter
Reply #1 - Dec 7th, 2010, 8:02pm
 
It comes purely from the spec of the standard you are designing your serial IO for.
Spec documents usually indicate jitter specification in terms of UI.
You choose a particular no. of cycles  to form that eye.
Hence, transmission speed/no. of cycles is the lower limit you start integrating your phase noise from. Highest frequency of integration depends on your ckt BW.
[i dnt know for which serial IO you are talking about but 20M is too less, i suppose.]

--M
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raja.cedt
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Re: Integrating limits for jitter
Reply #2 - Dec 7th, 2010, 8:26pm
 
hi mayank,
for many application default people use 20M. you check in the following doc. What do you mean by 20M is too low because if it is above the pll BW i think its fine. Could you please clearly explain on what factors lower and upper limits will depends?

I am talking about  PCI-1,2 serial IO applications.

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rajkumar palwai
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Re: Integrating limits for jitter
Reply #3 - Apr 19th, 2011, 4:03am
 
Hi
I think 20M is good enough for higher limit. Though i am not sure about the lower limit of 12KHz.

while setting the lower limit u need to think of the Receiver CDR BW too. The jitter in the Clock extracted from the CDR will have all the low freq noise that is present in data. Only after the CDR BW, the clock appears as ideal compared to the data and those high freq components appear in eye diagram

But i dont know how that 'magical number' 12Khz has come.

regards
rajkumar
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