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extremis

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Cascode Bias
Dec 13^th, 2010, 6:51am

I have replaced the 2nd stage of the classic 2 stage Miller compensated OPAMP with a cascode stage to get more gain, i have BIASed the top 3 MOS transistors to work at saturation for Vcm=VDD/2, but they get out of saturation range for higher/lower Vcm.

What is the best way to make it work for the entire Vcm range? Should i use a wide swing cascode mirror?

Thank you in advance for any suggestions.

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AnalogDE Senior Member Offline Posts: 137	Re: Cascode Bias Reply #1 - Dec 13^th, 2010, 10:42am Are you using a telescopic topology? If so, that topology has an inherently limited common mode input range -- consider using a folded cascode topology to increase VCM range.
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extremis

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Re: Cascode Bias
Reply #2 - Dec 16^th, 2010, 9:00am

No, it is not telescopic topology; first stage is a differential PMOS pair with NMOS mirror load. Instead of the NMOS common source with PMOS load second stage i have a cascode stage, but it is much more unstable.

I design the OPAMP so that Vout=(VDD+VSS)/2 for Vcm=(Vcm,max+Vcm/min)/2; Vout usually varies with Vcm, but with this topology it varies so much that one of the middle transistors gets out of the saturation range.

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AnalogDE Senior Member Offline Posts: 137	Re: Cascode Bias Reply #3 - Dec 16^th, 2010, 11:34am Got a picture of your opamp? You can't really control Vout with a high-gain amp unless you wrap feedback around it.
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extremis Junior Member Offline Posts: 10	Re: Cascode Bias Reply #4 - Dec 17^th, 2010, 2:42am I am trying this OPAMP from P.E. Allen lectures, except that input is a differential PMOS pair.
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Lex

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Eindhoven, Holland

Re: Cascode Bias
Reply #5 - Dec 17^th, 2010, 2:59am

extremis wrote on Dec 17^th, 2010, 2:42am:

I am trying this OPAMP from P.E. Allen lectures, except that input is a differential PMOS pair.

If you change the input (differential pair) to PMOS, and leave the output the same, you can get into biasing problems. If u want PMOS in, PMOS out, go for the folded cascode.
You can also make a complete PMOS->NMOS translation: NMOS diffpair -> PMOS diffpair AND PMOS outputstage -> NMOS output stage.

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extremis Junior Member Offline Posts: 10	Re: Cascode Bias Reply #6 - Dec 17^th, 2010, 3:25am I have already done the PMOS->NMOS translation; it is the BIAS that bothers me. I have used a wide swing cascode mirror to BIAS the top 2 PMOS transistors, but maybe there is a better solution that works for the entire Vcm range. I have also used a voltage divider to avoid complementary differential input.
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Lex

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Eindhoven, Holland

Re: Cascode Bias
Reply #7 - Dec 20^th, 2010, 1:23am

extremis wrote on Dec 17^th, 2010, 3:25am:

I have already done the PMOS->NMOS translation; it is the BIAS that bothers me. I have used a wide swing cascode mirror to BIAS the top 2 PMOS transistors, but maybe there is a better solution that works for the entire Vcm range. I have also used a voltage divider to avoid complementary differential input.

Biasing of transistor N3 will be poor around corners. You can improve by using a long diode connected transistor with a resistor to supply, to bias N3. =)

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