ontheverge wrote on Dec 14th, 2010, 12:41pm:Hi,
in a N-bit pipelined ADC, stage k for example, what should be the dynamic error requirement during its settling period for the MDAC? I think 1/(2^N) is over constrained. any thoughts on this?
thanks,
Steve
what makes you think that the requirement 1/(2^N) is too restrictive?
If you consider the systematic DNL introduced at the boundary of each quantization interval, then you will see that a finite settling accuracy dv will appear as +dv on one side and -dv on the other, giving you DNL = 2*dv, just due to finite settling errors (combination of finite DC gain + settling errors).
And that would be just the DNL from one single stage. If all your stages were identical, you would get input-referred DNL:
= (2*dv + 2*dv/2 + 2*dv/2^2 + ...)/2, where the assumption is that you are using a stage gain of 2. You can work out what dv needs to be in order to get whatever target DNL you want due to systematic errors alone, not counting other error sources.
Vivek