carlgrace wrote on Dec 17th, 2010, 3:16pm:Does anyone have any experience with deep nwell? Does it really help much for, say, a 12b 80MSPS pipelined ADC? I built one years ago in 0.25um CMOS without deep nwell. Now I'm building another in 65nm but I would prefer not to use deep nwell so I can reduce layout size. Do you guys think this is a mistake, or can I get away with it?
it's difficult to say. there are 2 points which come to my mind:
1. Improved isolation against substrate noise: This is probably the big advantage, although I don't know how good the isolation remains as you go faster and faster. Obviously, you need to use good shielding.
2. Impact ionization: If you are planning on using folded cascode, maybe with gain boosting to cut down on power in the amps, then you may run into issues with impact ionization in the N-cascode. Deep Nwell technology allows you to use a local P-well for the NMOS, permitting you to tie B-S together and avoid the Rout degradation, but depending on the topology you choose, this may or may not be relevant.
You need to consider the cost-performance tradeoff. The only times I used Deep-Nwell was when I anyway needed it for some other reason, like HV support, or when the technology used anyway happened to have it.
Vivek