Hi,

In order to reduce the WPE effects, it is generally advised to increase the distance from the transistors to the well edges. I'm wondering whether the substrate contacts also deteriorate the effects? e.g., for NMOS transistors, the substrate contacts have to be P+ implant - while forming the NMOS S/D, there should be photoresist to stop N+ implanting at the substrate contacts region (P+), thus introducing WPE effects  with the same way as the N-well?

Thanks for attention!
Ruri