The numbers you are getting seem reasonable from what I have seen.

What references are you seeing higher IIP3?

The primary 3rd order contributor is Ids nonlinearity as Vds increases, so anything you can do to minimize Ron should help to reduce nonlinearity (wider device, optimized LO drive and proper gate bias).

Also, make sure you are using a model that properly models nonlinearity at Vds_dc=0V. BSIM used to have some discotinuous functions around Vds=0 that yielded bogus linearity results. The PSP model used continous functions through Vds=0 and yield more reliable results. Although, maybe the BSIM model has been updated (I don't know).

Hi RFICDUDE and Aaron,

Thanks for replying.  Sorry , I didn't make it clear, in oder to have LO of 17dBm, I do need to use the thick oxide devices that can tolerate a voltage up 2.5V across the oxide.  

When I use the qpss and qpac to get my IIP3 plot, I have the same problem as Aaron posted before, i.e., the 3order slope looks weired at low input level.  Since my IIP3 is around 20dBm, my slope starts to act funny below 0 dBm.  I did use the conservative setting for running qpss, but it didn't seem to change my results that much.  In general, the slope seem to look ok for the top 20 dB input range.  In another word, if the IIP3 is 25dBm, then the 3 order slope starts to behave funny below 5 dBm.  So if you try to extrapolate the IIP3 at Pin < 5dBm,  you get pretty lousy number, not to mention the slope looks all wrong.

Do you guys think this is a simulation/modeling problem?  Or in reality, the IIP3 is that bad at the low input level?

Thanks much.
Kelly

Hi Vp1953,

The RF and IF are biasd  at 400mV to 600mV below the LO port (just right before the threshold).  I was  able to get pretty good conversion loss around -3ish over corner.  But my NF is around 8dB.  Any idea why the NF is not closer to the CL?  Is it just all device noise?

Not sure whether the attachment will show up

Here is the how the FETS are biased.  The resistor divider provides VCC/2 for the Gate.  The sources and drains are bias to a voltage thats 400mV below the gate (via the 4 resistors that are connected together)

Hi Aaron,

I looked at the noise summary they looks ok, no big surprise.  The top contributer is the 50 ohms inside the port.  The the 4 FETs.  If I take the input referred divided by the 4kt(50)/4 (4 is due to the resistor divider form by the 50 ohms source and the 50 ohms to ground at the RF port), I get roughly 8dB which is the same as the NF from Pnoise sim.  Yes, I am looking at SSB.

I did notice that there is a slight difference between the conversion loss (-2.85 dB) vs the transfer function from the NF calculation (around -4dB).  Don't know why the difference, but even with CL=-4, the NF is still 4 dB higher.

Do you usually see a much closer relationship between CL and NF?

Thanks.
Kelly

This is probably the problem that RFICDUDE mentioned earlier.

See: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1358719

Regards,

Andrew.