I need help with PLL phase noise simulation and analysis. Your comments and suggestions are appreciated.

I've built time-domain PLL behavioral models following the paper "predicting the phase noise and jitter of PLL-Based Frequency Synthesizers". I made a current mismatch in the charge pump block, and tried to find the output spur caused by this mismatch. After the tran simulation in hspice, I processed the output periods.m file with the matlab code in page 45 in the paper.
It seems to me the output spectre is up to the frequency fout/2 (fout is the VCO output frequency).
My questions are, am I right to simulate the spur using behavioral model?
How can I change the processing code in order to see the spur nearby fout?

Thanks.