For example, if metal 2 is horizontal and metal 3 should be vertical.
Is it because of parasitic capacitance?

Mostly its for simple routing, alternate N-S paths with E-W paths. (or up-down, left right)

Consequently, if you want to go anywhere on the chip, in theory, you only need to go thru one set of vias.

The reality of the matter is that lower metal layers tend to be used for routing inside a functional block, and upper metals get used between blocks in the system.

Vertical thickness of oxides is intentionally kept thick to minimize coupling between vertical layers, but some coupling does exist nonetheless.