we design a mixed signal chip with three main parts:
- sensible analog
- switched capacitor based adc
- logic part

all these parts are connected to a the padring, which build up by standard digital output cells, and ESD protected analog cells.

Now my question is - how should we seperate the power lines. I know we have to seperate vdd(digital) and vdda(analog) but what should i do with VDDA of SC Circuits and with the power of padring(digital outbut buffer and esd diode connection)

i want to minimize crosstalk and clockfeedthrough to all analog - and to ensure i high snr for adc.

Second question: Should i separate digital ground and analog grounfd, too? How i can to this becaus LVS notice the connection about substrat and give me an error,