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haykp Community Member Offline Posts: 40	Flip flop design Feb 14^th, 2011, 3:13am Dear Forum, The attached picture is a schematic diagram of a Dff. As can be seen in that diagram the first input TG clock is CL and not CLK. What is the reason of this? Why we cannot conect the CLK to the clock of first TG. Thanks, Hayk Petrosyan
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rfidea Senior Member Offline Posts: 159 Europe	Re: Flip flop design Reply #1 - Feb 14^th, 2011, 9:51am Probably to get some buffering and not loading CLK more than necessary.
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Rakesh Community Member Offline Posts: 60	Re: Flip flop design Reply #2 - Feb 14^th, 2011, 10:57am Probably for meeting hold time requirements or bufferening the input clock
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vp1953

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Posts: 172

Re: Flip flop design
Reply #3 - Feb 15^th, 2011, 9:09am

Hi Haykp,

You are saying CLK and CL could be used instead of CL and CL-bar. The circuit requires complementary clock signals. CLK is external and may have a large skew depending on the load on the driver; i dont know if there might be some issues using a skewed CLK and a non-skewed CL for the complementary clock signals. Using internally generated CL and CL-bar removes the external clock skew.

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Nandish Mehta

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Re: Flip flop design
Reply #4 - Feb 21^st, 2011, 8:23am

The main concern with all flip-flop design is the clock loading. It is one of the main design metric.

CLK routing and distribution tree already consumes hell lot of power. Add even one TG extra to CLK is majority of time not affordable. Hence CL & CLb are generated first.

If you go through the operation you will find that operation of F/F is still same as with CL or CLK.

Hope this helps
Regards
Nandish

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