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Nandish Mehta

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Mis Match analysis
Feb 19^th, 2011, 12:59am

Hi Friends,

I was doing mis-match analysis using Monte-Carlo on my folded cascode OTA.
My gain spec is 7K with UGB of 500MHz which I am able to meet under typical corner.

With process only, the variation in gain & UGB is still under control.
However, when I do mis-match analysis the whole design falls apart. The gain falls down to 1K and UGB goes in GHz range.
Can any one please help me with managing this mis-match?

Please provide your valuable suggestions and inputs.

Regards
Nandish

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rfidea

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Europe

Re: Mis Match analysis
Reply #1 - Feb 19^th, 2011, 1:16am

The mismatch will introduce a offset voltage at the comparator input. If you measure the gain and UGW with a pure voltage source at the input the comparator will be biased at the quiscient point. One way to solve this is to introduce some feedback in your testbench to make the comparator to be in its "middle" point where it has the largest gain.

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sheldon

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Re: Mis Match analysis
Reply #2 - Feb 19^th, 2011, 2:52am

Nandish,

� Is the amplifier still biased correctly when mismatch is included?
In particular, are the cascode devices still biased? You also did not
mention single-ended or differential, if the design is differential does
mismatch degrade the common mode loop?

� � � � � � � � � � � � � � � � � � � � � � � � � � � � �Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Sheldon

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Nandish Mehta

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Re: Mis Match analysis
Reply #3 - Feb 19^th, 2011, 3:13am

Thanks rfidea for your response !!!

If i use any trick like feedback in my test bench will it still give me a true mismatch. What i mean is in actual circuit which i will tape out will not have the feed back to fix the input bias but test bench will have.

Can i still estimate correctly what mis-match my chip might have with this test bench? Can you please comment on this? Like test bench might give very good matching but actual design might get screwed up.

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Nandish Mehta

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Re: Mis Match analysis
Reply #4 - Feb 19^th, 2011, 3:55am

sheldon wrote on Feb 19^th, 2011, 2:52am:

Nandish,

� Is the amplifier still biased correctly when mismatch is included?
In particular, are the cascode devices still biased? You also did not
mention single-ended or differential, if the design is differential does
mismatch degrade the common mode loop?

� � � � � � � � � � � � � � � � � � � � � � � � � � � � �Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Sheldon

Hi Sheldon,

The folded cascode ota has differential input and single ended output. (PMOS active load is diode connected on one side)

When mis-match analysis is ran the cascode is biased with constant drain current biasing whereas the input pair are biased by constant DC source to the respective input common mode.

Sheldon, can you please recommend some scheme for the input pair biasing so that I can keep the gm of these devices constant?

Thanks for your response. I think from your questions I have got a hint to solve my problem. It will be kind of you if you can suggest me some biasing scheme which are commonly used for input pair.

Regards
Nandish

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rfidea

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Posts: 159
Europe

Re: Mis Match analysis
Reply #5 - Feb 19^th, 2011, 6:20am

Hi Nandish!

There is no point in measure gain and UGW if the comparator is not biased in its linear region. A gain of 7000 and an offset of 1mV will saturate the output if the input is 0V. The only meaningful way of measureing this is to try to bias the input at Vos so the output is in the linear region. Feedback is probably the easiest. Your chip will work, but you will have an input offset voltage that gives an error when using the comparator. So you should have a specification for that voltage. You can measure this voltage in the testbench by using feedback and measure the voltage difference between the inputs.

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