Starting from 55nm technology, TSMC starting to provide MOM capacitor in generic CMOS technology such as 40LP.

My question is that whether TSMC do any special treatment on those MOM area, to improve the metal width/space accuracy? (which eventually improve capacitor accuracy) Or MOM cap is just a regular metal finger cap which a special layout pattern.  

Usually, finest metal spacing will cause metal-metal finger capacitor variation as large as about +/- 20% or even worse. I heard from the street that MOM capacitor accuracy can be within +/- 10%. I'm curious if this is real.

Thanks,
Neo