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Simulating trimming circuit - DC convergence issues (Read 3019 times)

rsmithuf

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Posts: 4
Dallas, TX

Simulating trimming circuit - DC convergence issues
Feb 22^nd, 2011, 4:19pm

Hi All,

Long time reader, first time poster. I have a complicated problem to try and explain but it relates to trimming a circuit.

Problem Statement:
I have a voltage-to-current circuit that takes a bandgap voltage across a resistor to create a current, then mirrors it. The resistor is trimmable since it has a temperature coefficient. The goal is to run my simulation over PVT and have a automated circuit find the optimum resistor setting to use.

V2I Circuit:

The current produced is 4uA.

The Testbench:

The top left is the V2I circuit. On the bottom right is an ideal current source with a tempco that is similar to the overall V2I. It produces an equivalent voltage across an ideal resistor. Ideally, it will always be 400 mV. A VCVS source compares an ideal source to the generated source to get an error signal. That error signal is fed into a verilog-A modeled 5-bit ADC (see attached).

The ADC is configurable to perform an inversion and/or 2's complement number. I currently have it set to 2's complement + inversion. The trim code is a 2's complement number (middle of the range is all zeros) and I want an inversion to cancel out the positive error slope being fed to it.

Here is a snapshot of the circuit working well when there is no feedback from the V2I:

At the bottom is the error signal being fed to the ADC and it is correctly providing a inverted digital code to the V2I. The very top signal (IS("/V5/PLUS") is the corrected 4uA output. As you can see, it is somewhat compensated, but not as well as I think it could be.

The problem occurs now if I directly connect the 4uA output of the V2I to the input of my tuning circuit (ie remove the ideal 4uA current source and replace it with one from the V2I). Now there is feedback in the circuit and for whatever reason, I cannot establish a DC operating point, nor a transient one. Can anyone suggest why and what I could do to fix this problem? Is there an easier solution to this?

I'm thinking I do not understand completely the way the VerilogA code is working and how/when it evaluates the expressions inside. I'm thinking that when the operating point does not converge, it is oscillating between two trim codes and never finding the optimum point. Maybe I need some sort type of hysteresis in the ADC or circuit to prevent this from happening and give up a little accuracy?

Has anyone done something like this or similar and can share with me what they did? I feel certain that this is a common problem that every designer has to solve.....

Many thanks - I'm tired of pounding sand.

veriloga.zip

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Marq Kole

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Hmmm. That's
weird...

Posts: 122
Eindhoven, The Netherlands

Re: Simulating trimming circuit - DC convergence issues
Reply #1 - Feb 24^th, 2011, 5:41am

Hi,

I've had a look at your Verilog-A code. I think there are several things you can improve:

In the contribution statements near the end of your model you are contributing piece-wise constant values. I would strongly suggest to use transition filters here. This will most likely solve your DC convergence problems already.
The case statements you use are a waste of simulation time as these will be equivalent to a 32 level deep if-else statement. In Verilog-A case does nto work by look-up, but by checking all conditions and picking the first that matches.
Instead of writing pow(2,bits) for creating an integer power of 2 you can much better do 1<<bits. That uses integer arithmetic and is way faster than the floating point pow() function.
You do not need to initialize variables to 0 in your initial_step event - they are 0 by default.
Put the code starting at counter until the last of the case statements inside an event statement. That can be as simple as:
Code:
```
prev_vin = vin;
@(initial_step or above(prev_vin - V(in)) or above(V(in) - prev_vin)) begin
... your code ...
vin = V(in);
end
 
```
Now your code will only be evaluated if it is the first time step or if there is a change in the input voltage.

Hope this helps.

Cheers,
Marq

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