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saam Community Member Offline Posts: 39 india	Metal layers in layout Mar 01^st, 2011, 1:59am Can anyone tell me ..why top metal layers in layout having high resistance compare to lower,,is there any analysis for this?? ThankU saam
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Metal layers in layout Reply #1 - Mar 1^st, 2011, 6:43am no top metals are always have less res because of its thickness and this is the reason why inductors have been made with top layers. Thanks.
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Lex Senior Member Offline Posts: 201 Eindhoven, Holland	Re: Metal layers in layout Reply #2 - Mar 1^st, 2011, 8:05am Not always true Raja. Some processes have copper at the bottom and alu and the top.
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saam Community Member Offline Posts: 39 india	Re: Metal layers in layout Reply #3 - Mar 2^nd, 2011, 7:56pm Thank U for reply � � But can u elaborate more, means in terms of analysis like using sheet resistance or�resistance formula. also can u give me any materials,books or any links �regarding how to use metal layers in layout Thanku saam
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loose-electron

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Re: Metal layers in layout
Reply #4 - Mar 3^rd, 2011, 8:58am

Metal layer thickness, metal used, oxide thickness between layers, are all able to be defined and selected by whoever defines and creates the foundry process.

Commonly used conventions are:
- Top layer is often thicker metal.
- Oxides are thick between layers (lower C coupling)

However, its all unique to the foundry process you are on.

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love_analog Senior Member Offline Posts: 101	Re: Metal layers in layout Reply #5 - Mar 3^rd, 2011, 10:58am Alexander, Why would anyone flip the metal layers. The whole point of putting copper was to increase EM reliability. I would think the top layer metals would always carry more current since they are carrying it from the pads.
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Lex

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Re: Metal layers in layout
Reply #6 - Mar 4^th, 2011, 5:01am

love_analog wrote on Mar 3^rd, 2011, 10:58am:

Alexander,

Why would anyone flip the metal layers. The whole point of putting copper was to increase EM reliability. I would think the top layer metals would always carry more current since they are carrying it from the pads.

Circuits that benefit from a thinner stack use copper at the bottom as copper can be thinner in height.

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saam Community Member Offline Posts: 39 india	Re: Metal layers in layout Reply #7 - Mar 6^th, 2011, 1:39am ThankU for replies.. can anyone provide materials, books or any links regarding metal routing in analog layout. waiting saam
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saam Community Member Offline Posts: 39 india	Re: Metal layers in layout Reply #8 - Mar 6^th, 2011, 8:46pm Can anyone tel me ..Why top metal layer (M8) has low resistance compare to bottom (M1) ??? ThankU saam
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ACWWong Community Fellow Offline Posts: 539 Oxford, UK	Re: Metal layers in layout Reply #9 - Mar 7^th, 2011, 4:42am Maybe its thicker or of a different material. Check your process manual for data. For formulae on resitivity just google it. For methods of layout, Alan Hasting's book Art of Analog Layout is good.
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saam Community Member Offline Posts: 39 india	Re: Metal layers in layout Reply #10 - Mar 8^th, 2011, 9:30pm Thank You ACWWong...i wl
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rfmagic

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Re: Metal layers in layout
Reply #11 - Mar 9^th, 2011, 6:22am

Hi saam,

As most of the guys have mentioned, the first thing you have to do is to find out the process paremeters of your foundry. Then you can start
estimating the zero order parasitics of the layout i.e. comulative sheet resistance, cumulative capacitance of the traces and inductance of the metal layers. this can help you get started.
I have created a simple spreadsheet a long time ago that does these simple calculations and you may find it useful.

Enjoy.

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Parasitic_estimation.rar

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loose-electron

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Re: Metal layers in layout
Reply #12 - Mar 10^th, 2011, 10:48am

love_analog wrote on Mar 3^rd, 2011, 10:58am:

Alexander,

Why would anyone flip the metal layers. The whole point of putting copper was to increase EM reliability. I would think the top layer metals would always carry more current since they are carrying it from the pads.

Increase EM reliability?

Total news to me, and I was involved with the Cu CMP process at the time.

Copper got added to drop the R down, to get faster RC time constants to allow higher clocking rates.

Jerry

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loose-electron

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Re: Metal layers in layout
Reply #13 - Mar 10^th, 2011, 10:52am

saam wrote on Mar 6^th, 2011, 8:46pm:

Can anyone tel me ..Why top metal layer (M8) has low resistance compare to bottom (M1) ???

ThankU
saam

Unique to process as others have stated, but commonly its because they make the top layer thicker.

If its all copper CMP layers, you have very good control over the characteristics of the layer thickness.

The PDR's are fussy so that you can avoid cupping/dishing issues, when doing the CMP planarization of the layers.

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Jerry Twomey
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saam Community Member Offline Posts: 39 india	Re: Metal layers in layout Reply #14 - Mar 20^th, 2011, 10:40pm Thank you for all...:) for such a great discussion
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