[quote author=eleckymess link=1300988590/0#0
Code:@( condition 1 )
V(a,b) <+ c;
end
[/quote]
The "@" is what makes this an analog event.
Quote:It uses NC Verilog simulator, right?
NC Verilog is a digital Verilog simulator; you are using AMS, so I think you probably have Spectre running this module.
Quote:Here I got confused. As far as I know, a contribution statement can actually be used only in an analog event, and it is used to assign an expression to a voltage or a current at a port or branch. I think any real number or any parameter as used in my code is a legitimate expression. If I am right, what's wrong with my code?
You may be thinking digitally. The analog block of an AMS module is evaluated at every timepoint of the transient analysis. On some of those timepoints, the @(analog_event) will fire, and the simulator would try to make the contribution, but on other timepoints, what do you want to happen?
You probably want something like
Code:@(initial_step)
vout = 0;
@( condition1)
vout = c;
V(a,b) <+ transition(vout);
where now, the contribution is not conditional: it always establishes a voltage-source branch between a and b, but the voltage it enforces varies.