Hawick
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Hi loose-electron, Thanks for your reply! But I still don't understand that. My pipeline adc consists of front-end SH, four pipeline stages with 2.5bits/stage, 2bits flash adc.
My question is: 1. Assumed INL and DNL have been known. when I simulate each stage, what requirement does the output residue of each stage meet?
2. The following is my idea. full scale=2V, resolution=10bit, INL=+-0.3LSB Typical corner,INL=0.3LSB=0.3*2/(2^10)=0.6mV definition: the contribution of each stage's error to ADC's INL sample and hold is I0 from stage1 to stage4 respectively is I1, I2, I3, I4 Then , The INL referred to the input of the ADC is found by dividing each INL by the gains preceding the
stage being studied. I0+I1/4+I2/16+I3/64+I4/256=INL distribute the contribution of each stage to INL I0=1/2INL, I1/4=1/4INL, I2/16=1/8INL, I3/64=1/16INL, I4/256=1/32INL so, INL=(1/2+1/4+1/8+1/16+1/32)=31/32INL then, I0=1/2INL=0.3mV I1=4*1/4INL=0.6mV I2=16*1/8INL=1.2mV I3=64*/16INL=2.4mV I4=256*1/32INL=4.8mV
the above result is the maximum error of output residue of each stage. I think my idea is wrong. But I don't kown what is the right one. Thanks! Best regards, Hawick
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