I would like to hear peoples thoughts about the best location for an RF power amplifier in an SoC.  

I am floorplanning an RF transceiver with a power amplifier that sinks ~350mWatt of quiescent power.  I can place the PA either in the corner of the die or in the middle along one edge.  Which is best?

In both locations there is plenty of room for multiple ground and Vdd bondwires.  The CMOS SoC is somewhat large and contains considerable digital real estate.  My main concern is about die stress, reliability and getting the heat out.  Is one location better than the other for these issues?

Thanks,
Makelo