Probably means the long term jitter when the PLL output frequency is at 200MHz(just a guess).

PLLs output jitter variance increases with time upto ~ 1/bandwidth and then flattens out assuming a jitter free reference. This could refer to the flattened out variance.

The period jitter of an oscillator is (the variance of) how much each each period varies from the average period T0. Similarly, you can define the variance of how much the duration of N periods of the oscillator differs from N*T0. The variance of this will be higher. (For an open loop VCO with white noise sources, it'll be N times higher). For a PLL, the variance increases as N increases and flattens out after N*T0 exceeds the bandwidth of the PLL. I assume your spec is for some large N in this range.

Nagendra