In principle, you could use a parameter (but NOT a variable); see this example:

http://www.designers-guide.org/VerilogAMS/functional-blocks/data-converter/conve...

module adc (out, in, clk);
   parameter integer bits = 8 from [1:24];      // resolution (bits)
...
   input in, clk;
   output [bits-1:0] out;

However, I'm not aware of any simulator that supports this; they all need the number of terminals of the adc to be known before parameter processing.