Hi everyone,

As I understand the native devices have lowest threshold close to zero, better matching and also low noise like flicker due to low doping.

Why is it that then not many designs use them for design of analog circuits like opamps in advanced tech. such as 65nm or 90nm where we have low voltage headroom?.

I have searched online and read through many documents but none of them clarify why native is not preferred over standard or low Vt? Can anyone explain this perhaps in relation to an opamp as an example.

Many Thanks

Hi Alexander,

Like I said, my understanding comes from what I read in other forums and few papers found on IEEE. So it might be that I am wrong which is why I post my question here.

Usually there is no need of  additional mask in creating native transistors since it is formed directly on the substrate. (I quote this from a IEEE paper that I found). Even if an additional step is needed this should only increase the fabrication costs which I am not concerned with here. I am more interested in its use for building analog blocks assuming costs are not a factor.

Matching relates to how the transistors are uniform in there properties and I think the uniform doping of the substrate allows only small variations between transistor parameters like in case of a curent mirror.
I dont understand what you mean by modelling. Do you mean the model parameters provided by the foundry?
From the lecture material provided in the website of Prof. Philip E. Allen it is given that native transistors allow increased ICMR in an opamp when characterized. Did you mean this that the transistors are not characterized properly?


The usefulness of the native transistor is something I am not sure about since I have not found many papers using it.  
This is why I put of the question here so experienced forumites might answer.
As I have never used it or created layouts from it so haven't got a clue as to whether creating layouts is hard or easy.

I don't get what's wrong with using 0-vt (native) transistors in a current mirror configuration.  In my process they have a lower mismatch coefficient.  As long as I can bias them with a good enough overdrive what's the issue here?  They should work better since Vth=0 leaves more headroom.

I simulated a comparator across PVT and they seemed to work fine.  They are biased in saturation.

Hi AnalogDE,
Did you try minimum Vt corner?
Remember Vds > Vgs - Vt requires Vt > 0 for standard current mirror topology.
B O E

Some background:

Threshold on CMOS can be anything you want it to be.

Anything. It is selectable by the implant doping under the gate region. This is very much a foundry controlled thing. (Also affected by the dielectric of the gate oxide and thickness of the oxide)

PMOS/NMOS thresholds are typically set at 25% to 35% of the voltage between Vdd and ground.

Why these threshold levels?
Logic Design - it gives the best logic immunity to false logic states due to ground bounce and power rail dips.

So called "native" transistors, used to also be known as "depletion" transistors, where the Vth could be near zero, or even negative. (You had to hold the gate to a negative voltage on NMOS to keep the thing turned off)

My experience with foundries has shown that the generic transistors that are commonly used in the digital design are the best controlled, most accurately modeled, devices, just due to foundry priority.

Because of the above fact, I try to avoid using the "native" devices. Better matching? Perhaps, but they data collected needs to be questioned.