nadroit,

To many things to mention, but as a colleague of mine once said simulate any "career  limiting" events.  ESD and latchup are forgivable events, but startup, incorrect logic hookup, unwanted oscilations, non oscilations when wanted.  These are the things that can reduce the momentum of ones career discredit a small company.

1. Simulate supply ramp up from zero to full dc
2. Transient steady state with no signal, then a supply step transient, then wait to see if an oscilation appears.
3. Verify that communication from the comms interface is seen at the destination of intended logic.

There are many specific to your architecture sims that are not as general as this, hope this helps.

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nadroit,

If you don't have any ESD circuitry then I would not tape out until you do. 0.13uM oxide is thin and could breakdown during the sawing up of the wafer just from the friction, long before you have parts in hand.  There are two standard components for ESD protection.

1.Two reverse biased diodes between supply and ground connected to the signal leaving the IC
2. Supply clamp

It is common for the ESD for high frequency IO's to have a limited protection, ie smaller diodes, but some protection is required.   check your design kit documentation, most foundries provide some standard ESD.

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ESD in an RF front end is a big part of the system.

You must have ESD
However, ESD can effect the performance of an RF front end in a big way

If you have never taped a chip out, you need to partner with an experienced designer for some guidance. Without that it could be an expensive learning experience.

Hi,

If you are using a MPW company for the tapeout, it is often a good idea to ask them to fully check the design too.  My experience is that if you specifically ask, they will run DRC, ERC, etc.  It is always good to have a second check.

This is interesting ... as far as I know the TSMC 0.13 do come with some ESD cells (diodes and clamps).

Are you going through MPW ?

Here are a few more general tips :-
a) Power supply routing - ensure low resistance and wide enough tracks
b) Metal fill ... some foundries put them in for you ... usually where you don't want them. Specify keepout areas. At 10GHz, it may be significant.
c) Biasing ... biasing ... biasing. Ensure your bias startup circuits DO startup (and do not oscillate). If you have space, put in some means for external biasing. Note that in the beta multiplier, if you take the degeneration resistor off chip, you run the risk of oscillating it due to excess parasitic cap.
d) Device and Via Spares - make sure you have some scattered around empty spaces. You may need to use them in a metal re-spin.

the list goes on ...

ps : hope you have not taped out yet !