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surreyian

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PMOS and NMOS output resistance
May 18^th, 2011, 1:39am

Hello all,

the output resistance is given as
1) satuation region, R=1/(Lamda*Id).
2) linear region, R=1/[u.Cox.(w/l).(vgs-vth)]

In these cases, PMOS will have higher outout resistance as PMOS has lower mobility and Id. Is my understanding correct?

However in Razavi's design of analog CMOS integrated circuit, chapter 2. It states that for given dimensions and bias current, NMOS has higher output resistance. How does this statement come about?

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RobG

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Re: PMOS and NMOS output resistance
Reply #1 - May 18^th, 2011, 8:29am

surreyian wrote on May 18^th, 2011, 1:39am:

Hello all,

the output resistance is given as
1) satuation region, R=1/(Lamda*Id).
2) linear region, R=1/[u.Cox.(w/l).(vgs-vth)]

In these cases, PMOS will have higher outout resistance as PMOS has lower mobility and Id. Is my understanding correct?

However in Razavi's design of analog CMOS integrated circuit, chapter 2. It states that for given dimensions and bias current, NMOS has higher output resistance. How does this statement come about?

I've never investigated this issue, but output impedance is only important in the saturated region, and there is no mobility term in your equation for that region. [edit - sorry, mobility is in the Id term, I see what you are saying about how the PMOS should have high Rds]

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« Last Edit: May 19^th, 2011, 8:21am by RobG »

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boe

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Re: PMOS and NMOS output resistance
Reply #2 - May 19^th, 2011, 8:02am

RobG wrote on May 18^th, 2011, 8:29am:

surreyian wrote on May 18^th, 2011, 1:39am:

Hello all,

the output resistance is given as
1) satuation region, R=1/(Lamda*Id).
2) linear region, R=1/[u.Cox.(w/l).(vgs-vth)]

In these cases, PMOS will have higher outout resistance as PMOS has lower mobility and Id. Is my understanding correct?

However in Razavi's design of analog CMOS integrated circuit, chapter 2. It states that for given dimensions and bias current, NMOS has higher output resistance. How does this statement come about?

I've never investigated this issue, but output impedance is only important in the saturated region, and there is no mobility term in your equation for that region.

Surreyian,
Note that for equal Id, the small signal resistance rds = 1/(Lambda*Id) depends on the constant, which is different for nMOS and pMOS.
Also note that you need more overdrive for the pMOS to achieve the same current assuming equal-sized MOS transistors - in this equation the mobility is hidden in the current.
B O E

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dxt78 Junior Member Offline Posts: 15 Ohio	Re: PMOS and NMOS output resistance Reply #3 - May 19^th, 2011, 8:09am Razavi's statement does seems confusing, and there was some previous discussion on this here: http://www.designers-guide.org/Forum/YaBB.pl?num=1115223850
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: PMOS and NMOS output resistance Reply #4 - May 19^th, 2011, 11:33am hi, current depends on number of electrons passing through area per sec. So mobility indicates speed of the electrons but number of electrons also matter .. Thanks.
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dxt78

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Re: PMOS and NMOS output resistance
Reply #5 - May 19^th, 2011, 9:19pm

raja.cedt wrote on May 19^th, 2011, 11:33am:

hi,
current depends on number of electrons passing through area per sec. So mobility indicates speed of the electrons but number of electrons also matter ..
Thanks.

I thought from RobG's post we were assuming equal ID for the NMOS and PMOS. This would address the "number of electrons" issue you bring up. The output resistance would then be entirely dependent on lambda, which is a device level parameter that would depend on the doping of various regions right?

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: PMOS and NMOS output resistance Reply #6 - May 19^th, 2011, 11:37pm hi, i agree but o/p resistance so called ro is not a device parameter, in fact its derived parameter just to indicate vds effect on current. have you added r0 noise in any simulation? the ans is no because its not physical resister which mainly depends on channel length. Thanks.
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dxt78

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Ohio

Re: PMOS and NMOS output resistance
Reply #7 - May 20^th, 2011, 6:41am

raja.cedt wrote on May 19^th, 2011, 11:37pm:

hi,
i agree but o/p resistance so called ro is not a device parameter, in fact its derived parameter just to indicate vds effect on current. have you added r0 noise in any simulation? the ans is no because its not physical resister which mainly depends on channel length.

Thanks.

Right I agree it's not a device level parameter. But we are discussing which has a larger output resistance, NMOS or PMOS. If the current through each is equal, then aren't differences in output resistances determined solely by lambda?

So I guess the question is what has a small lambda, NMOS or PMOS? And what determine the lambda of a device?

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