chris2312
New Member
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Posts: 6
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Hello,
I'm new in design of integrated circuits. I have to design a lna. I choosed cascode topology to achieve high gain at high frequencies. My problem is to find a bias point with minimum noise of the transistor. I have red that most lna's operate iun class-A, so you have to choose the bias current that Ic = Icmax/2. Othwerwise the shot noise oft the transistor will increase with high current, so i choosed a bias current which is smaller than Icmax/2. I plotted gm vs. NF to find a good tradeoff first for a common emitter stage. Now I want to do the same for the cascode to find an optimum, but I have no idea how to realize it, because of the bias voltage of the load transistor. Can you give me some hints ? Thanks for response.
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