Hello,

I'm new in design of integrated circuits. I have to design a lna. I choosed cascode topology to achieve high gain at high frequencies. My problem is to find a bias point with minimum noise of the transistor. I have red that most lna's operate iun class-A, so you have to choose the bias current that Ic = Icmax/2. Othwerwise the shot noise oft the transistor will increase with high current, so i choosed a bias current which is smaller than Icmax/2. I plotted gm vs. NF to find a good tradeoff first for a common emitter stage. Now I want to do the same for the cascode to find an optimum, but I have no idea how to realize it, because of the bias voltage of the load transistor. Can you give me some hints ? Thanks for response.

Hi Chris 2312

I do not think LNA's operate like Class A power amps. Even before you get to zero current (due a large RF signal), there are some many issues relating to nonlinearity etc that prevent typical usage at high input power levels. There are some good examples in Tom Lee's book (most of which you can read online). Rfcooltools has provided a good summary of what needs to be done to reach noise-gain targets

RF front ends are not a good place to have  learning experiences in IC design.

If it is for any typical RF front end, it is going to have to have a Class A structure to meet linearity requirements.

Do you have:
Noise spec
Linearity Spec
BW spec
Gain Spec
defined source impedance
defined output load

min max criteria on all, IP2, IP3 specs for linearity?

thats some of the very basic stuff you need before you get started.

vp1953 wrote on May 30^th, 2011, 5:54pm:


Almost always Class A for linearity - Never say never!

purplewolf,

many bjt foundries provide the peak ft as a component display parameter after running a DC operating point. Additionally ft can be approximated as gm/((Cbe+Cbc)*2*pi).  

http://rfcooltools.com