Hi all,

I am trying to understand the one-one corresponding of the linear SFG of a first oder Sigma delta ADC with its  circuit implementation.  as shown in figures below

the integrator shown in Fig 32.7 is a delaying discrete analog integrator with   TF = Z^-1 /( 1 - Z^-1)     when considered from its inp to output

If the comparator has a delay of half cycle (Z^-0.5)  total loop TF  would be differnt from what the linear model in Fig32.6  shows.


one possibilty which can work is if the discrete analog integrator has TF = Z^-0.5/(1 - Z^-1)   and comparator  with Z^-0.5


So can we really  use a comparator which has TF =(Z^-1 )    (where the preamplification and regeneration happen in consecutive half cycles   )   while making a stable loop and  a modulator?   









thanks,
yvkrishna

The loop delay is one cycle. opamp output=y; comparator output=v=sgn(y)=y+e.
y[n-1]: end of previous phi2
y[n]: end of this phi2
v: sign of y sampled at the rising edge of phi1 or, equivalently, the end of previous phi2

Therefore, y[n]=y[n-1]-v[n-1]; This gives the desired NTF.

There is no one to one correspondence between the block diagram and the schematic. The delay for the input signal is half cycle in the latter and one cycle in the former. This makes a difference to only the STF and is irrelevant.

For details, see, e.g. http://www.ee.iitm.ac.in/~nagendra/EE658/200908/lectures/20091027/20091027.html