Hi all,
I am trying to understand the one-one corresponding of the linear SFG of a first oder Sigma delta ADC with its circuit implementation. as shown in figures below
the integrator shown in Fig 32.7 is a delaying discrete analog integrator with TF = Z^-1 /( 1 - Z^-1) when considered from its inp to output
If the comparator has a delay of half cycle (Z^-0.5) total loop TF would be differnt from what the linear model in Fig32.6 shows.
one possibilty which can work is if the discrete analog integrator has TF = Z^-0.5/(1 - Z^-1) and comparator with Z^-0.5
So can we really use a comparator which has TF =(Z^-1 ) (where the preamplification and regeneration happen in consecutive half cycles ) while making a stable loop and a modulator?
![](http://C:\Users\vkyakala\Desktop\firstOrdSDM.png)
thanks,
yvkrishna