I want to design a integer N CML based divider for PLL. The VCO will be designed later. The output frequncy of VCO will be around 1.5 GHz. I want to know whether the input waveform for divider simulation should be a sine wave or a square wave. I strongly beleive that the output of divider is square wave which is input to PFD but not sure about input waveform.
If it is a square wave, how to generate such wave at high frequencies without noise performance.

Hi Purplewolf,

You are feeding the output of the VCO to the divider?If the VCO is LC tank based, then the output should be sinusoidal - it should be fine to feed this sinusoidal input to the input of the CML based divider.

hi purplewolf,
i want to add some thing to above points.
1. As far i know for for an cml divider if you give sufficient swing it's fine, for mosfet based divider you should have min swing is 1.414*Vov and for a bjt based structure 3 to 4 VT.
2.is vco signal is getting buffered by some level converter, because this is going to add jitter (because this is the general case for any vco which has provision for testing.)?


Thanks.

hi,
but in your first post you said you are ging to design CML divider, now you are saying that it is simple digital circuit.

Thanks.

No man..be clear. CML is completely  different than cmos. So your divider is digital one so then whats he question of wave shape. You should use square wave by buffering VCO through some level converter.

Thanks.

Hi Purplewolf,

For dual modulus 8/9 prescaler that uses CML, input is sinusoidal and output can also be sinusoidal. You can of course convert the output of the VCO to a square wave to feed to the divider, but at much higher power consumption - why would you want to do this?

If you search around for some papers, you should find entire schematics for aCML 2/3 or 4/5 dual modulus prescalers, which can easily be extended to 8/9

It sounds like a classical case of a digital guy talking to an analog guy, and neither understands the other.

First, if you have 1.5G, you'll probably need a special CML or buffer to get to CML for a couple divisions.  This will start as a sinusoid and be square after a divider or 2.  You need to define what frequency this is at.

Now, I'm not sure it makes sense (power wise) to continue dividing 8 or 9 times in CML.   While you could stay in CML --- you might be better off converting CML to CMOS, where you can run standard cells and RTL flow.

So again, I think the VCO and CML designer needs to step up first and give a spec as to what is getting divided at which frequency.
Ditto with the Refclk and input divider.

Wave

Hi Purplewolf,

For phase frequency detectors, generally they are edge triggered either positive or negative, so duty cycle is not important here.

For a pure phase detector (as in an XOR gate), duty cycle is very important.