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Using rfmos or mixed-mode mos in the design of RF frequency divider (Read 6690 times)
YCY
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Using rfmos or mixed-mode mos in the design of RF frequency divider
Jun 23rd, 2011, 7:15pm
 
Hi,

I am using a 55-nm CMOS process to design a 4-GHz CML frequency divider using cascade 2/3 cells and
confused about which model, the rfmos or mmmos, should I use in the pre- and post-layout simulation.

Because the rfmos has four metal stacked on the source and drain and its gate is also connceted using metal3,
the physical size is very large (about 10x of mmmos). Thus I use the mmmos in the circuit layout.
However, since the model of mmmos dose not support to rf frequencies (as far as I know, it's model supports no higher than 2GHz),
it may lead to a too optimistic result even after the post-layout simulation.

Although the rfmos is more suitable for high-frequency circuit,
its huge physical size makes it impossible to be used in divider's layout.
Besides, the rfmos's large parasitic capacitance always leads to an over design
which consumes much more current than that of mmmos.

So can anybody share your experience in designing RF dividers?
and which cell, rf or mmmos is better that will make a compact and accurate design?

Thanks.
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rfcooltools.com
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #1 - Jun 24th, 2011, 12:31pm
 
YCY,

When you say mmmos are you referring to the baseband (nonRf) model of that foundry if so here is what I would do.
The RF devices are probably well characterized by the foundry. So I would start by designing the divider with the rfmos this way you can get a better idea of what you would expect with parasitics.   then make the change to their nonRf mos layout and RCextract.  You will likely see a similar result.  Or another way you could do it is to RCextract  the device you would likely use and use it as a subcircuit in place of mos device in your schematic.  

It has been my experience that the bulk of the parasitics is at the device level, for some reason the foundry does not do a better job of getting the pre-layout close to the post layout for nonRF on these deep sub-micron nodes.

http://rfcooltools.com
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YCY
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #2 - Jun 24th, 2011, 4:37pm
 
Hi, rfcooltools.com

Thanks for sharing your experience, and as you said,
the mmmos I mentioned before is the baseband model.

Actually, the method you said (using rfmos in pre-layout
and nonrf mos in post-layout simulation) is the way we usually do in our company.  
But the simulation results in the two cases are always quite different.
Take my design for example, the RCextract baseband mos can operate at
4 GHz within 1 mA, while the rfmos consumes almost 2mA.
That's why I said rfmos leads to an overdesign in the beginning.
The big difference makes me confused. I am not sure which result
I should trust. Could you share your experience about how large the difference is?  

BTW, you said "the bulk of the parasitics is at the device level".
Do you mean the parasitcs are mainly from devices rather than metal routing?
 
Thanks,

YCY.
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purplewolf
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #3 - Jun 24th, 2011, 5:10pm
 
For the high frequency synchronous section of the divider you must use rfmos devices. for asynchronous part and the counters you can use ordinary devices as they work at lower frequency.
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rfcooltools.com
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #4 - Jun 24th, 2011, 6:55pm
 
YCY,

in the example you site what was the actual outcome? 1 or 2 mA

I usually spend a little amount of time proving to my self that the extraction is believable in the beginning of using a kit for the first time.  For example the RF devices usually have somewhere in the model guide measured vs modeled.  So if I take the exact same device and extract it I should get a similar performance. Usually this is the case but sometimes they differ.  There are a few reasons why this might be, one is that there are settings in the capacitance/resistance look up table generation that when generated might not contain the right resolution to be able to resolve certain geometries correctly.   Typically an over estimation is the result in this case, but it could go the other way.  The goal is always to find a reasonable path back to a measured result, because modelling is mostly, but not always accurate.  

Step 1: check the accuracy of your extractor against measured data.

Check that your extractor follows the correct behavior when for example your adjust the pcell so that your source/drain are pushed apart.  The extractor should follow a logical decrease in the source to drain capacitance depending on distance.  If not then step 1 might be a coincidence.  Get a  RFdevice or two to match and your confidence in the tool should increase.

If you believe that it all makes sense then you may want to construct a new model of prelayout devices using a wrapper of some sort to try to predict the post layout.  Again believing in the extractor come up with a scalable model for this.  Why the foundry can't do this For regular devices I don't know, but that is what it is.  

Step 2: try to estimate your parasitics at pre layout

Finally be discriminating of results that don't make sense either good or bad.  Most errors occur from believing results to good to be true.   Try look at measured results as a a way to refine your simulation test bench.  

These are just a few points obvious or not which may help you get more predictable results.  

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YCY
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #5 - Jun 24th, 2011, 11:24pm
 
Hi, rfcooltools.com

Thanks for your suggestions. They really help a lot,
yet I still need to figure out one thing: In the first step,
which pcell do you mean to be extracted? rf mos or regular mos?

Since rf mos is an hcell that will be skipped in the extractor,
I don't  think I can extract its parasitics in the extractor. Or in other words,
the foundry believes they has provided a complete model that we don't have
to  extract the rf devices any more.

As for the regular device, the layout is quite different from the rf devices.
Comparing their data with measured ones at high frequencies doesn't seem to make sense?

Again, thanks for sharing your experience, I really appreciate that.

Sincerely,

YCY.  
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« Last Edit: Jun 25th, 2011, 4:10pm by YCY »  
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rfcooltools.com
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #6 - Jun 25th, 2011, 10:56am
 
YCY,


Step 1: check the accuracy of your extractor against measured data.
a. flatten RF PCELL and remove the LVS RF device identifier layers, without these layers LVS should see this as a baseband device. LVS it against a base band device and you should be clean then extract.
b. Simulate this extracted view  against the RFModel and compare.
c.  Move the source and drain spacing on a regular MOS device and C only extract at different distances, netlist each extracted and compare csd,ssb,cdb,cgs,cds.  Are they changing with hand calculations?

If step1 is not within a reasonable margin of error consider exploring another more manual fitting method

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YCY
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Re: Using rfmos or mixed-mode mos in the design of RF frequency divider
Reply #7 - Jun 25th, 2011, 4:07pm
 
Hi, rfcooltools.com

Thanks for your detailed description.
That would be very clear now.

YCY.
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