The delay behaves as a phase delay with unity gain. The mathematical description is exp(-i*2*pi*f*T). The delay will lower your phase marginal with its phase delay at your loopgain crossing frequency. For example, if your crossing frequency is 1GHz and your delay is 0.1ns you will lower the phase margin with 360*0.1n*1G=36deg.

hello allr,
yes, i agree with formula.

1. we can say that delay will decrease phase margin, So can i conclude by increasing slightly delay in the loop will give better settling time (if system has better phase margin before introducing delay)
2. I have  so much replica delay in pll feedback path, now i want to introduce some delay in behavior model.  How to introduce that (i know that some how we have to  introduce e^-st)

Thanks,
Raj.

hi rfidea,
i am using spectre circuit simulator and there some how i am modeling every block  with vcvs and vccs

Thanks,
raj.

hello buddypoor,

I am guessing through some intuition. Please find the attached plot. Here let say you have given 1v signal, output will reach K volts and feedback voltage will be 1. Now if you apply 0 volts, O/P has to reach 0 . So steeling depends on the forward path integrator now. If you have any delay it will keep fb voltage still 1 so that integrator will see 1 volt and it decelerates fastly, where as if you have don't have any delay changes at the o/p will immediately reflect at input. Please note that in the above analysis i am assuming that delay is small such that it won't make your system unstable.

Buddypoor some how i am trying to derive some expressions but i am not able to..can you give any suggestion, whats the final Goal is without delay in the loop gain we will get some poles, but with delay may be poles which are far from with delay case.

Sorry for the big post.

Thanks.

raja.cedt wrote on Jul 4^th, 2011, 2:21am:



Hello raja.cedt

I am very sorry but I do not understand what your problem is now.
I don't get the meaning (problem description) of the first part and also not the more general question at the end of your posting.

Let me state the following: I assume you know about the meaning of the loop gain and the stabilization criterion (Nyquist) associated with it.
Because in this respect the phase plays a major role, of course any delay effects within the loop are very critical because they introduce additional phase shifts into the loop. And this phase shift is proportional to the frequency!
That means - as far as the integrator with a delayed feedback is concerned (your example):  The circuit is stable only if the unity-gain frequency of the integrator is smaller than the frequency that introduces an additional phase shift of -90 deg due to the delay element. This results in a total phase shift of -180deg (plus -180 deg due to neg. feedback at the summing node).
Does this answer some parts of your question?

raja.cedt,

The system you show is analyzed in detail in the first few lectures at the link below. You get a delay differential equation whose solutions are (combinations of) exp(st) as usual. Explanation and analysis of this in time domain give a quick intuition to all results regarding negative feedback amplifiers and delay.

http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=ee539_2011:start

Quick summary of responses to a step:

* zero delay: exponential build up with a time constant 1/omega_u

* delay < 1/e/omega_u: Equivalently a two pole system(two real solutions for s); No overshoot---equivalent to overdamped two pole system

* delay = 1/e/omega_u: Two identical solutions for s; Fastest step response without overshoot---equivalent to critically damped two pole system

* 1/e/omega_u < delay < pi/2/omega_u: Infinitely many complex conjugate solutions for s, all in the left half plane; The lowest frequency solutions dominate---equivalent to underdamped two pole system

* pi/2/omega_u = delay: Infinitely many complex conjugate solutions for s, with at one pair on the imaginary axis; unstable

* pi/2/omega_u < delay: Infinitely many complex conjugate solutions for s, with at least one pole pair in the right half plane; unstable

* A "reasonable" amplifier without too much ringing while settling: delay < 0.5/omega_u

A real system with many parasitic poles behaves quite similarly to this. Graphs are shown in the videos at the link above.

Alexandar, linearizing exp(-s*tau) as 1/(1+s*tau) doesn't give the small signal response. The approximation is OK for very small delays, but gives incorrect results for critical damped case etc. and doesn't predict instability for any value of tau. linearizing it as (1-s*tau) does predict instability, but again at the wrong value of tau I believe.

Cheers
Nagendra


Nagendra

Lex wrote on Jul 5^th, 2011, 4:26am:



Just for clarification: The above formula is identical to the Pade-Approximation as I have mentioned in my posting before.