hello all,
i guess many people are aware of the current mode driver what i have shown in the attached fig.
1.My first question, is tail node cap impacts return loss, i think ans is yes because when one data is high one side of the output pad will connected to tail node directly. Can any please ans this query?

2. If Return loss depends on tail node cap how to simulate this?  because when people are simulating RL, in their setup they have total pad and data will be either high or low. In this kind simulation setup you don't see tail node moving, hence that incremental cap is zero. so If simulation have to taken care of this tail node cap we should give full data like 10101 pattern and do some kind of PAC analysis.
I am new to this drivers so got this kind of doubt.

Hope some will clarify this.

Thanks.