In RF PLLs, frequency dividers normally have very high division ratio. In a Fractional-N PLL, the division ratio are in the range of several hundreds, while in an Integer-N PLL, the division ratio is around several thousands even tens of thousands.

To make things worse, frequency dividers are quite often designed to operate with square wave like wave form. Thus, even more harmonics need to be included in the simulation (be it HB or time domain shooting).

Depending on frequency divider topologies, sometimes it can be broken down and simulated part by part (pulse swallow counter for one), sometimes it can't.

Now the question is, for those frequency dividers which can't be broken down, how do you simulate their phase noise? I often saw people simulate for example a multi-modulus divider at very low division ratio to make the simulation less expensive and converge. But I think it is somehow flawed, since at higher division ratio the MMD is actually running, the clock goes through different path and switched by different transistors.